The ability to provide relatively inexpensive miniature digital cameras based on semiconductor imaging devices has opened up a wide range of new imaging applications.
There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCD technology is often employed for image acquisition and enjoys a number of advantages which makes it the incumbent technology, particularly for compact imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques.
However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read-out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with CCD arrays, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel which results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices and for use in ultra-compact imaging applications.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate or photoconductor. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994), as well as U.S. Pat. Nos. 5,708,263 and 5,471,515, which are incorporated herein by reference.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD because standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
One application for a CMOS imager is in a swallowable capsule imager. Although swallowable (ingestible) capsule imagers have potential for providing significant diagnostic information, they do have limitations. Traversing the human gastrointestinal (GI) tract by peristatltic action typically takes about 10-24 hours. Accordingly, it would be advantageous to have an ingestible system in which the power supply would last long enough for the imager to pass through to the end of the colon, or which could be operated on novel low-power supply systems.
Also, the natural peristaltic transport is unidirectional and, in current systems, images are generally reviewed after passage of the pill, not in real time. Thus the quality of every captured image is important. Accordingly, it is desirable to have advanced image control including exposure control.
Further it is desirable to communicate environmental parameters and system parameters in the video stream thus avoiding additional transmission circuit complexity. Still further, it is desirable to make a self-contained system that is readily reconfigurable as new applications become available. These advanced operations and the operational flexibility are difficult to achieve in the basic ingestible capsule imager.
The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-29 (1994); Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(2) (1997); and Eric R. Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95, pp. 17-25 (1995) as well as other publications. These references are incorporated herein by reference. Additional disclosure related to the operation of one exemplary CMOS imager is found in U.S. Pat. No. 6,376,868 to Howard E. Rhodes issued Apr. 23, 2002 and in U.S. Pat. No. 6,333,205 to Howard E. Rhodes issued Dec. 25, 2001.
One of the problems in miniaturation of CMOS imagers while providing imager control flexibility is the number of discrete integrated circuits which must be used to form an operative imaging system. Three to eight separate chips are typically used for the imager sensor array, the controller, and other ancillary circuits which form the imager system. The use of separate discrete circuits is particularly problematic when one uses the imager in the environment of a swallowable pill where overall device size is of concern. In addition, having discrete circuits to perform different operations of the imaging system also consumes battery power, which is again in the environment of a swallowable pill.